The present invention relates generally to an exposure method, and more particularly to an optimization of an exposure condition.
A conventional projection exposure apparatus uses a projection optical system to expose a reticle (or mask) pattern onto a plate, such as a single crystal substrate for a semiconductor wafer, and a glass plate for a liquid crystal display. In order to meet a demand for inexpensively supplying many electronic apparatuses, a method for manufacturing a device, such as a semiconductor chip (e.g., an LSI, a VLSI), a CCD, an LCD, a magnetic sensor, and a thin-film magnetic head), needs to improve the yield rate. This device manufacturing method includes various processes, such as exposure, development, and etching. In exposure, a conventional exposure apparatus considers not only the resolution at which the reticle pattern precisely resolve on a plate to be exposed, but also the influence on the other processes in the device manufacturing method.
The optimizations of both the exposure condition and the reticle pattern are important for improved resolution. See, for example, Japanese Patent Applications, Publication Nos. 2005-26701 and 2002-319539. A reticle pattern is optimized, for example, through an optical proximity correction (“OPC”). A critical dimension (“CD”) uniformity is known as a general conventional evaluation index of the resolution. See, for example, Japanese Patent Applications, Publication Nos. 2003-257819 and 2005-094015. Japanese Patent Application, Publication No. 9-319067 proposes a technology, called a process proximity control (“PPC”), which adds an etching error caused by the pattern density, to a reticle design in advance so as to correct the etching error. A simulation or a simulator may be used instead of actually exposing the plate for effective optimizations.
Other prior art include, for example, SPIE 5379-15 Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology and Evert Seevinck, Frans J. List, and Jan Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Vol. SC-22, NO. 5, October (1987). The above SPIE reference discloses a via chain as a test pattern under various design rules, measures the resistance, and determines whether the design rules and the OPC are properly set.
As finer processing advances, an interaction between processes in the device manufacturing method becomes non-negligible, and the yield rate control over exposure only using the CD uniformity cannot necessarily improve the yield rate. Whether or not the device is defective as an electronic component depends upon the electrical characteristic of the device. A typical example of the electrical characteristic is a power supply voltage characteristic that is defined as a voltage change of the device to the power supply, but the electrical characteristic may be durability, resistance, electric capacity, etc.
For a static RAM (“SRAM”), an illustrative electrical characteristic includes a static noise margin (“SNM”) (see the above IEEE reference), VTH difference in a transistor gate, etc. The electrical characteristic to be verified differs according to device types.
However, the evaluation index relating to the resolution does not always correspond to the electrical characteristic. For example, even when the CD uniformity is bad, the device is not defective in view of the electrical characteristic, and even when satisfying a predetermined CD uniformity, the device is defective in view of the electrical characteristic.